01 / analytical engine
Compute first.
Parses structured engineering data, compares artifacts, extracts relationships, runs rules, and keeps the numerical and semantic foundation deterministic.
SilTest Semiconductors
Deterministic AI for semiconductor engineering.
VISTAR™ turns specs, test programs, STDF data, debug logs, and engineering documents into traceable actions for chip test, production, yield learning, migration, and knowledge capture.
Every output is backed by engineering evidence you can review.
INPUTS
- Specs · RTL · IJTAG
- ATE programs · STDF
- Logs · patterns · limits
Graph + AI
Reasoning Core
Reasoning Core
OUTPUTS
- Conversions + reports
- Debug hypotheses
- Yield actions + traceability
Traceevidence backed
Reviewengineer in loop
Deployprivate by design
100%
deployed on your own infrastructure
<5 min
from raw STDF to a yield answer
100%
on-prem, your data never leaves your fab
Why now
Faster engineering decisions, with evidence you can review.
Semiconductor work is deterministic: limits, bins, test semantics, patterns, logs, and production evidence must remain reviewable. AI is useful for language and synthesis. Engineering intent needs domain grounding and human review, and VISTAR is built around both.
What slows teams down
- Engineering knowledge is scattered across specs, scripts, logs, tickets, spreadsheets, and tester programs.
- ATE migration and test collateral generation still depend on manual interpretation.
- Yield and debug teams spend too much time finding context before acting.
What VISTAR™ changes
- Creates an engineering graph that connects artifacts, rules, and relationships.
- Uses analytical engines for deterministic computation and AI for synthesis, explanation, and orchestration.
- Produces traceable outputs that engineers can inspect before use.
Platform architecture
Three parts, one engineering platform.
VISTAR™ combines deterministic analysis, generative synthesis, and agentic workflow execution in one governed semiconductor AI layer.
02 / generative AI
Explain clearly.
Turns extracted engineering context into readable reports, summaries, migration notes, debug explanations, and review-ready outputs.
03 / agentic AI
Execute workflows.
Coordinates tools, searches evidence, prepares artifacts, flags gaps, and routes work to humans when judgment or sign-off is required.
Engineering sourcesSpecs · RTL · register maps · IJTAG · ATE · STDF · logs
↓
VISTAR™ knowledge graphentities · relationships · constraints · traceability
↓
AI + deterministic toolsrules · agents · LLMs · validators · domain workflows
↓
Reviewable outputscode · reports · actions · evidence packs · management views
VISTAR™ is a non-disruptive intelligence layer over your existing workflow.
One secure engineering layer connects your data, domain rules, AI agents, and human review across the semiconductor lifecycle.
Knowledge graphDomain rulesEvidence linksReview gatesPrivate deployment
VISTAR™ modules
Focused modules that share one platform foundation.
Test Program Generator, AutoMigreX, SightFiX and CertOptiX are available today. Modules marked Roadmap are in development, and further module names in the lifecycle map below belong to that roadmap.
Generation
Test Program Generator
Generate and review test collateral from specifications, register maps, test intent, and platform constraints.
Migration
AutoMigreX
Convert and compare tester programs and pattern formats with explainability and validation artifacts.
Compliance
CertOptiX
Map the compliance work you actually perform, trace each activity to the requirement behind it, and see where effort is duplicated or over-controlled.
Standalone
YieldOptiX + DefectOptiX
Our standalone tools connect to the platform. Run YieldOptiX analytics by prompt inside VISTAR, and feed DefectOptiX quality models with production data.
Debug
SightFiX
Guide debug sessions by linking symptoms to test flow, limits, logs, historical issues, and likely next checks.
Role-based lifecycle map
See where VISTAR™ helps across the full SoC lifecycle.
Select a role to highlight the phases, artifacts, and VISTAR™ applications most relevant to that stakeholder, from product requirements through design, verification, DFT, production ramp, and end-of-life learning.
01
Strategy
Market need & product requirements
Capture customer use cases, product constraints, safety/security needs, cost targets, and early testability expectations before architectural decisions harden.
02
Concept
SoC architecture & feasibility
Compare architecture options, IP reuse, DFT risk, verification scope, power/performance/area tradeoffs, and manufacturing assumptions.
03
Planning
IP selection, reuse & project plan
Map IP dependencies, ownership, review checkpoints, integration risks, verification intent, and acceptance criteria into a traceable execution plan.
04
Definition
Microarchitecture, register model & interfaces
Connect requirements to block architecture, register maps, bus protocols, DFT hooks, coverage points, and reviewable design intent.
05
Implementation
RTL design & SoC integration
Assist with RTL consistency checks, interface assumptions, integration deltas, DFT collateral alignment, and cross-artifact traceability.
06
Verification
Simulation, assertions & coverage closure
Prioritize failing tests, correlate logs with requirements, explain coverage gaps, summarize regressions, and preserve debug evidence.
07
DFT planning
Scan, MBIST, LBIST & IJTAG strategy
Translate product and architecture constraints into test strategy, access architecture, coverage goals, pattern assumptions, and review checkpoints.
08
DFT implementation
DFT insertion & collateral generation
Support DFT rule checks, IJTAG access modeling, pattern intent, generated collateral, waivers, and semantic consistency across tools.
09
Pre-silicon
Emulation, prototype & debug closure
Connect failures, waveforms, logs, configuration data, test intent, and design context into ranked hypotheses and reusable debug notes.
10
Sign-off
Physical integration & tapeout readiness
Prepare decision packs that connect design intent, verification closure, DFT coverage, waivers, known risks, and release evidence.
11
ATE
Test program generation & migration
Generate, convert, compare, and explain tester collateral across platforms while preserving measurement intent, limits, bins, flows, and APIs.
12
Bring-up
Silicon debug & first-lot learning
Connect STDF, fail signatures, logs, test programs, lab observations, and design/verification history into evidence-backed debug hypotheses.
13
Qualification
Reliability, guardbands & release gates
Track qualification evidence, guardband decisions, test escapes, excursions, and release readiness across lots, corners, and product variants.
14
Ramp
Manufacturing ramp & yield stabilization
Turn raw production data into Pareto views, excursion alerts, root-cause candidates, correlation studies, and engineering action lists.
15
Production
Mass production, quality & cost learning
Monitor drift, recurring failures, retest behavior, bin movement, tester/site effects, and product health signals for continuous improvement.
16
Lifecycle
Field returns, EOL & lessons learned
Preserve product knowledge, connect lessons learned to future designs, reduce expert dependency, and build a reusable semiconductor learning system.
Full lifecycle view
All phases are visible. Use the role pills to highlight what each stakeholder sees first.
16 phasesVISTAR™ app layerReusable learning loop
Proof by workflow
Real workflows, on your own data.
Real-world examples of how VISTAR™ turns your existing data into useful tools and insights.
Inputs
Product requirements
RTL / DFT / IJTAG
ATE programs
STDF / yield / logs
Knowledge graph + agents
VISTAR
Maps engineering intent, retrieves evidence, applies deterministic workflows, and produces reviewable outputs.
Outputs
Migration reports
Root-cause ranking
Spec conversion
Production learning loop
Specrequirements and registers
Generatetest intent + collateral
Convertplatform migration
Validatediffs and reports
Learnyield and debug feedback
Deployment and protection
Built for companies that cannot send silicon data to public AI services.
VISTAR™ is designed and built for controlled, highly complex semiconductor environments where IP, customer programs, tester data, and production evidence must remain protected.
Secure data boundary
On‑prem or private cloud.
Use open-source models and private infrastructure where required. Keep chip data, test programs, logs, and STDF files inside your environment.
Governed outputs
Human in the loop.
Separate suggestions from sign-off. Produce reports that engineers can inspect, compare, and approve before production use.
Engineering traceability
Evidence over assertion.
Every meaningful answer should point back to source artifacts, transformations, assumptions, and validation checks.
Credibility
Built by semiconductor engineers, for semiconductor engineering teams.
One European automotive IDM automated lot release on the VISTAR architecture: around 5 NPI engineers had spent 50 to 60% of their time on releases, and today 1 engineer runs it, supported by a system that works 24/7.
Domain depth
DFTATPGMBIST / LBISTIJTAG / IEEE 1687ATESTDFDiagnosticsYield engineeringAdvanced nodes
How to engage
Start small with one workflow. Prove value on a controlled project. Expand into a reusable engineering knowledge layer after the first measurable result.
Technical demoPoCEngineering servicesAcademyPrivate deployment
Services and academy
Software when it can scale. Experts when the problem needs hands.
Engineering services and training that help your team move faster.
Engineering services
Hands-on execution.
DFT, test, migration, debug, and production support for projects where expert intervention is still required.
SilTest Academy
Upskill teams.
DFT, ATE, production test, yield learning, and AI-assisted engineering workflows for engineers and managers.
Focused tools
Adopt gradually.
Start with one use case, for example STDF viewing, migration support, or debug intelligence, before a wider platform rollout.
Start with your data
See VISTAR™ on a real engineering problem.
Bring one controlled workflow: tester migration, STDF yield analysis, debug intelligence, specification conversion, or project knowledge graph creation.
Suggested first demo
- One representative artifact set
- One measurable engineering outcome
- One reviewable output pack